199.3.5 Examples of test orders

1.
Test LTU2 of LTG1
Input:
TEST-TSU:LTU,1,2;
Output:
SWU-LTG (A HALF / ACTIVE)
TEST : SPEECH HIGHWAYS; ANY TIME SLOT
ADVISORY: NO IDLE SIU RECEIVER FOUND
HWY: LTG = 1 LTU = 2 HWY = 27
TRANSMITTER:LTG = 1 LTU = 7 SLOT = 13 FUNCTION = 2
2.
Test the CC-active (active system half of the common control)
Input:
TEST-TSU:CC,ACT;
Output:
SWU-CC (A HALF / ACTIVE)
TEST : MEMORY; RELEASE 2-BIT ERROR
ERROR : HARDWARE SUPERVISION CIRCUIT CANNOT BE RELEASED
ADDRESS = 118/32424
The address of the defective memory cell is made up of the number of the 64K block in which it is located (in order to determine the module concerned) and the offset within the block. Both are represented as decimal values.
3.
Test of a PNT (Private Network Terminator) of a SLMU16 board with PEN LTG=1, LTU=3, SLOT=61, CCT=2 and LOOPBACK=2
Input:
TEST-TSU:T,PEN,1,3,61,2,2;
Output:
TEST : SPECIFIED CIRCUIT; SPECIFIED TERMINAL
4.
Test of a Cornet-T device of a SLMU16 board with the number STNO=3567 and SERVICE=VCE or with PEN LTG=1, LTU=3, SLOT=61, CCT=2, LOOPBACK=4 (STD) and TSI=1
Input:
TEST-TSU:T,STNO,3567,VCE;
or
TEST-TSU:T,PEN,1,3,61,2,,1;
Output:
SWU-LTG (A HALF / ACTIVE)
TEST : SPECIFIED CIRCUIT; SPECIFIED TERMINAL
5.
Test of all devices of a S0-bus with PEN LTG=1, LTU=3, SLOT=61, CCT=2 and LOOPBACK=4
Input:
TEST-TSU:T,PEN,1,3,61,2,4;
Output:
SWU-LTG (A HALF / ACTIVE)
TEST : SPECIFIED CIRCUIT; ALL TERMINALS
TEST : SPECIFIED CIRCUIT; ALL TERMINALS
ADVISORY: TEST IS NOT ALLOWED
TERMINAL : LTG = 1 LTU = 3 SLOT = 61 NO = 2 TSI = 2
TYPE = SLMU16
TEST : SPECIFIED CIRCUIT; ALL TERMINALS
ADVISORY: TEST IS NOT ALLOWED
TERMINAL : LTG = 1 LTU = 3 SLOT = 61 NO = 2 TSI = 3
TYPE = SLMU16
.
.
.
.
TEST : SPECIFIED CIRCUIT; ALL TERMINALS
ADVISORY: TEST IS NOT ALLOWED
TERMINAL : LTG = 1 LTU = 3 SLOT = 61 NO = 2 TSI = 8
TYPE = SLMU16
The test for Cornet-T device TSI=1 was successful. The test is not allowed for functional devices TSI=2 to 8.
Note
Each test result message consists of at least two parts (A and B) and occasionally three parts (A, B and C). A successful test without errors consists only of one part (A).
A) TEST : Detailed test job executed
B) ERROR : Negativ result from the test A)
Object couldn’t be tested
C) ADVISORY : Additional data reported by the RTO
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