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5.26.6. Notes/Experience Previous topic Parent topic Child topic Next topic

There are many ways in which a route providing the reference clock can fail. In the simplest case it is only interrupted and the clock immediately switched off. The clock generator then switches to hold over mode. Regulation commences automatically in the case of interruptions of under 1 sec. An appropriate message is entered in the REFTA error column. If the interruption is longer than 1 sec., the security equipment is switched on. A waiting period of 1 minute is observed for the line to return and then regulation is restarted. If the interruption is longer than 1 minute, the next line with a suitable priority and error counter is selected from the REFTA and switched on.
Error cases with uninterrupted lines and deteriorating quality are more difficult. These could be caused by a repeater that is about to fail but is still delivering its own - internal inexact - clock or by external interruptions that result in higher jitter. A certain period of time can elapse before the clock generator detects the quality deterioration or the frequency departure. The "BAD CLOCK" error message provides valuable information.
If S2 or S0 lines are to supply the reference clock, SMD must be set to "NO" in the AMO SYSPAR. This sets the interface to TMD = Trunk Mode Digital.
If OpenScape 4000 systems are networked with S0 connections, the parameter SMD must be set to "NO" (despite priority = 0) in the AMO SYSPAR. This sets the layer 1 of this BA to permanent activity. Both sides of the connection must be set to "Trunk".
ATM interfaces will require that the interface is operated as a trunk with regard to the clock, although the board only addresses subscribers.
If a system has trunk connections to various carriers (Telecom, CMI, Viag, Telalliance, ...) it is more favorable to use different DIUS2, DIUN2 or DIUT2 records (or similar) than to put all (and different) carriers onto a single board. This not only provides better availability but also better synchronization: the reference clock to the clock generator has less jitter (cross-talk on a board) because the clocks of the different carriers can be only pseudosynchronous in the best case.