199.3.3
Test orders
Test orders:
T1
Test an LTG-active or LTG-standby including all speech highways to
the CSN-active.
This job consists of the linked jobs T3 (for the LTG-active control), T5 and
T8 to T11.
T2
Test the CC-active or the CC-standby
T2.1
Test the firmware of the controller area
T2.1.1
Interrogate the interface processor (IP)
T2.1.2
Interrogate the cross channel (CCH)
T2.1.3
Interrogate all message buffer units (MBUs)
T2.1.4
Interrogate all central input/output controllers (IOCCs)
T2.2
Test data processor (DP) module (=base processor)
T2.2.1
Release hardware supervision switch for multibus timeout on theDP module.
T2.2.2
Release hardware supervision switch for watchdog counter 0 on the DP module.
T2.2.3
Release hardware supervision switch for watchdog counter 1 on the DP module.
T2.2.4
Interrogate ready line to the partner DP module
T2.3
Test memories (common memory and local memory)
T2.3.1
Test memory allocations in CC-active or CC-standby
A parity check is carried out by reading all memory cells on all M8M memory
modules (MEMs) and on the MDP3DM, MDP486-DYN and MDP486-STA. A READ-WRITE
test is carried out on the DPML, MDP386-8M and the MIP.
T2.3.2
Interrogate all 1-bit error indicators on all M2M memory modules
T2.4
Test IEC bus between CCH modules; only for CC-standby
T3
Test the group control of an LTG-active or LTG-standby
The test job is rejected, if the LTG specified is not configured
or not present.
T3.1
Test the firmware of the controller area
T3.1.1
Interrogate the input/output controller of the group processor (IOCG)
T3.1.2
Interrogate the data communication link (DCL)
T3.2
Interrogate the data processor (DP) module (=group processor)
T3.2.1
Release hardware supervision switch for multibus timeout on the DP module.
T3.2.2
Release hardware supervision switch for watchdog counter 0 on the DP module.
T3.2.3
Release hardware supervision switch for watchdog counter 1 on the DP module.
T3.3
Test memories (common memory and local memory)
T3.3.1
Test memory allocations in an LTG-active or LTG-standby
The test job is rejected, if the LTG specified is not configured or not
present.
A parity check is carried out by reading all emory cells on all m M8M memory
modules (MEMs) and on the MDP3DM, MDP486-DYN and MDP486-STA.
A READ-WRITE test is carried out on the DPML, MDP386-8M and the MIP.
T3.3.2
Interrogate all 1-bit error indicators on all M2M memory modules
T4
Test a specific LTU in an LTG-active
The test job is rejected, if the LTU specified is not configured
or not present.
In SP390/391 the test job is also rejected, if the LTG
spcified is not configured or not present.
T4.1
Test a specific LTUC
T4.1.1
Test the microprocessor of that LTUC
T4.1.2
Test one timeslot on all highways to the specified LTUC
The timeslot selected will always be in READY status and idle (i.e. not busy)
T4.2
Test all modules of the LTU specified (without LTUC)
This job consists of a multiple callup of the job T6 by the RTO.
In contrast to an operator callup of the job T6, a specific module
is only tested if the module status is "READY".
T5
Test the board highways on a LTU shelf
T6
Test a specific line circuit module, SIU periphery module
All jobs affect modules in LTUs. However, the two modules of a "service unit"
(SU) are not tested, although configured at the LTU number 5.
T6.1
Test a specific line circuit module
The job is started if the module
• is contained in customer’s system configuration
• is present
• is plugged into the correct slot
• is not hierarchically blocked (by a superordinate device),
e.g. if the LTU is not defective or manually blocked.
T6.1.1
Interrogate the microprocessor of the line circuit module
T6.1.2
Test all line circuits of the line circuit module specified
The line circuit is only tested if the following conditions are met:
• The circuit is ready and not seized (idle).
• The circuit is in "line alarm" status, e.g. if the circuit
is not connected or the connection is faulty.
• The terminal (which can be directly connected or connected
via CTE) is defective or manually blocked.
• There is no terminal connected (either directly or via CTE).
• The circuit itself is faulty or manually blocked.
• The line circuit module is manually blocked.
T6.2
Test a specific module in the SIU periphery
The job is started if the module
• is contained in customer’s system configuration
• is present
• is plugged into the correct slot
• is not hierarchically blocked (by a superordinate device),
e.g. if the LTU is not defective or manually blocked.
T6.2.1
Interrogate the microprocessor of the specified module in the SIU periphery.
T6.2.2
Echoplex the specified module in the SIU periphery (loopback test from all
code transmitters to all code receivers of the module).
Only those code transmitters and receivers are tested which are
tested which are ready and idle.
T7
Test a line circuit
P7.1
Test SLMR, SLMR24:
The possible Loopbacks are as follows:
- interne loopback for voice (SLMRV)
- interne loopback for data (SLMRD)
Test TMD24, T1DN, TMDN :
The Test has to be performed on circuit 1 for both Boards.
any other circuit will be rejected.
The possible Loopbacks are as follows:
TMD24 :
- internal local loopback (ILOC)
- activate internal remote loopback (IDC)
this loopback is used in conjunction with EDC only.
- deactivate internal remote loopback (IDL)
this loopback is used in conjunction with EDC only.
- external remote Loopback (EDC)
This test must be performed in multiple steps.
a) the circuits of both local and remote Boards
must be deactivated via AMO-
DSSU
.
b) on The remote T1 the internal remote loopback has
to be activated with LOOPBACK = IDC.
c) Test for EDC (external remote loopback) can be performed
now on the local T1 board.
d) after output of the test result the internal remote
loopback on the remote Board has to be released with LOOPBACK = IDL.
TMDN / SLMN-T1 :
- internal local loopback (ILOC)
- activate internal remote loopback (IDC)
this loopback is used in conjunction with EDC only.
- deactivate internal remote loopback (IDL)
this loopback is used in conjunction with EDC only.
- external remote Loopback (EDC)
This test must be performed in multiple steps.
a) the circuits of both local and remote Boards
must be deactivated via AMO-
DSSU
.
b) on The remote T1 the internal remote loopback has
to be activated with LOOPBACK = IDC.
c) Test for EDC (external remote loopback) can be performed
now on the local T1 board.
d) after output of the test result the internal remote
loopback on the remote Board has to be released with LOOPBACK = IDL.
- activate internal remote payload loopback (IPON)
- deactivate internal remote payload loopback (IPOFF)
T1DN
- internal local loopback (ILOC)
- activate internal remote loopback (IDC)
this loopback is used in conjunction with EDC only.
- deactivate internal remote loopback (IDL)
this loopback is used in conjunction with EDC only.
- external remote loopback (EDC) same process as for the TMD24.
- internal digital loopback (SMIDIG)
- internal analog loopback (SMIANA)
Test RLI
The possible Loopback is as follows:
- data channel loopback (RLITDM)
(voice channel loopback is not possible here, see Notes)
STMA-TFA / STMA-PSW
- Loop 1
Test of other boards
Loop number is defined by the internal testroutines.
T8
Test of circuits (as in T7) but using defined highway and timeslot number
(after the test a ’hanging’ timeslot (half path connection) is released)
T9
Test the standard SIU in an LTG-active
T9.1
Interrogate the microprocessor of the standard SIU
T9.2
Echoplex the standard SIU by loopback test from any SIU transmitter to the
appropriate receiver.
The transmitter/receiver pair selected will be in ready status and idle.
T9.3
Transmit an external dial tone to the standard SIU and echo from
any timeslot on any dial tone receiver.
The timeslot selected will be ready and idle.
T9.4
Transmit cadenced tones (busy tone and internal dial tone) to the
standard SIU and echo from any timeslot on any dial tone receiver.
The timeslot selected will be ready and idle.
T9.5
Echo a test signal sent by any code transmitter of an SIU peripheral (SIU
Type 2) in any LTU from all code receivers of the standard SIU.
The code transmitter selected and the receivers tested will be ready and idle.
T10
Test the CONF module in an LTG-active (not possible on 80CMX-LC)
T10.1
Interrogate the microprocessor of the CONF module
T11
Test all timeslots on all speech highways between an LTU and the
GSN of an LTG-active (not possible on 80CMX-DSC)
Only those timeslots are tested which are in ready status and idle.
T13
Test a Cornet-T device (STNO, SERVICE and TESTYPE=SELFTEST),
a hole Workstation (STNO and TESTTYPE=SELFTEST),
a Rolmphone Selftest (STNO and SERVICE=VCE and TESTTYPE=SELFTEST),
a DCM / Optiset Selftest (STNO and SERVICE=DTE
and TESTTYPE=SELFTEST),
a DCM / Optiset looptest (STNO and SERVICE=DTE and
TESTTYPE=LOOPBACK).
a Check alive test on an Optiset terminal
(STNO, SERVICE=DTE and TESTTYPE=CHKALIV);
or a Linepower test on an Optiset terminal
(STNO, SERVICE=DTE and TESTTYPE=LINEPOW);
Test all terminals on a circuit (OBJECT=ALL),
Test of one terminal (OBJECT=SINGLE),
a Cornet-T device (STNO, SERVICE and TESTYPE=SELFTEST),
a hole Workstation (STNO and TESTTYPE=SELFTEST),
a Rolmphone Selftest (STNO and SERVICE=VCE and TESTTYPE=SELFTEST),
a DCM / Optiset Selftest
(STNO and SERVICE=DTE and TESTTYPE=SELFTEST),
a DCM / Optiset looptest
(STNO and SERVICE=DTE and TESTTYPE=LOOPBACK).
a Check alive test on an Optiset terminal
(STNO, SERVICE=DTE and TESTTYPE=CHKALIV);
or a Linepower test on an Optiset terminal
(STNO, SERVICE=DTE and TESTTYPE=LINEPOW);
T14
Test a specified PCM line
T16
Start of an external loop at DIUS2, DIUS7 or SLMN-E1 board for jitter
measurements
T17
Test of connection between WAML board and ADP
T18
Line testing on SLMA boards
- Test loop for subscriber in state onhook (ONHHOOK)
- Test loop for subscriber in state offhook (OFFHOOK)
T19
Test the modem for IPDA survivability connections
T20
Test the IPDA survivability path
T21
Test the modules on LTUCC board used for central byte manipulation
OpenScape 4000 V10, Volume 1: AMO Descriptions, Service Documentation, Issue 5
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P31003H31A0S107057620
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